1. Field of the Invention
The present invention relates to a power voltage sensing circuit. More particularly, the present invention relates to a power edge detector.
2. Description of the Related Art
Usually, power edge detectors are utilized to sense operations termed "power up" and "power down" in the application of analog or digital circuitry. In the power up mode, the power edge detector receives an input power voltage, generating an enable output signal when the input power voltage has exceeded a predetermined threshold level. Before that, when the input power voltage is below the predetermined threshold level, the power edge detector generates a disable output signal to disable certain portions of the circuit to prevent uncertain function due to either voltage level or system noise. In the power down mode, the power edge detector generates the disable output signal when the input power voltage falls below the predetermined threshold level, thereby assuring that certain critical portions of the circuit are disabled when the power supply goes below the predetermined threshold level and preventing uncertain function due to voltage level or system noise.
However, conventional designs implement the power edge detector by means of complex circuit structures that are suitable only for specific applications.